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dram module kmm372f213ck/cs i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle, t hpc . * note : dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 * i cc2 i cc3 * i cc4 * i cc5 i cc6 * i i(l) i o(l) v oh v ol symbol speed kmm372f213ck/cs unit min max i cc1 -5 -6 - - 990 900 ma ma i cc2 don t care - 100 ma i cc3 -5 -6 - - 990 900 ma ma i cc4 -5 -6 - - 810 720 ma ma i cc5 don t care - 30 ma i cc6 -5 -6 - - 990 900 ma ma i i(l) i o(l) don t care -25 -5 25 5 ua ua v oh v ol don t care 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : edo mode current * ( ras =v il , cas cycling : t hpc =min) : standby current ( ras = cas = w =vcc-0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in vcc+0.3v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out vcc) : output high voltage level (i oh = -2ma) : output low voltage level (i ol = 2ma) recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +1.3v/ 15ns, pulse width is measured at v cc . *2 : -1.3v/ 15ns, pulse width is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 3.0 0 2.0 -0.3 *2 3.3 0 - - 3.6 0 v cc +0.3 *1 0.8 v v v v absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -0.5 to +4.6 -0.5 to +4.6 -55 to +125 9 50 v v c w ma
dram module kmm372f213ck/cs capacitance (t a = 25 c, vcc=3.3v, f = 1mhz) item symbol min max unit input capacitance[a0-a10, b0] input capacitance[ w0 , w2 , oe0 , oe2 ] input capacitance[ ras0 , ras2 ] input capacitance[ cas0 , cas4 ] input/output capacitance[dq0 - 71] c in1 c in2 c in3 c in4 c dq1 - - - - - 20 20 45 20 20 pf pf pf pf pf ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v . see notes 1,2.) test condition : v ih /v il =2.0/0.8v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 131 155 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 18 20 ns 3,4,5,14 access time from column address t aa 30 35 ns 3,10,14 cas to output in low-z t clz 8 8 ns 3,14 oe to output in low-z t olz 8 8 ns 3,14 output buffer turn-off delay from cas t cez 8 18 8 20 ns 6,11,12,14 transition time(rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 18 20 ns 14 cas hold time t csh 36 43 ns 14 cas pulse width t cas 8 10k 10 10k ns 13 ras to cas delay time t rcd 18 32 18 40 ns 4,14 ras to column address delay time t rad 13 20 13 25 ns 10,14 cas to ras precharge time t crp 10 10 ns 14 row address set-up time t asr 5 5 ns 14 row address hold time t rah 8 8 ns 14 column address set-up time t asc 0 0 ns column address hold time t cah 8 10 ns column address to ras lead time t ral 30 35 ns 14 read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8 read command hold time referenced to ras t rrh -2 -2 ns 8,14 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 18 20 ns 14 write command to cas lead time t cwl 8 10 ns data set-up time t ds -2 -2 ns 9,14 data hold time t dh 13 15 ns 9,14 refresh period(2k ref.) t ref 32 32 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 36 40 ns 7 ras to w delay time t rwd 71 83 ns 7,14
dram module kmm372f213ck/cs test condition : v ih /v il =2.0/0.8v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max column address to w delay time t awd 48 55 ns 7 cas precharge time to w delay time t cpwd 53 60 ns cas set-up time( cas -before- ras refresh) t csr 5 5 ns 14 cas hold time( cas -before- ras refresh) t chr 8 8 ns 14 ras to cas precharge time t rpc 3 3 ns 14 access time from cas precharge t cpa 33 40 ns 3,14 hyper page cycle time t hpc 20 25 ns 12 hyper page read-modify-write cycle time t hprwc 68 77 ns 12 cas precharge time(hyper page cycle) t cp 8 10 ns ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 35 40 ns 14 oe access time t oea 18 20 ns 14 oe to data delay t oed 18 20 ns 14 output buffer turn off delay time from oe t oez 5 18 5 20 ns 6,11,14 oe command hold time t oeh 13 15 ns w to ras precharge time(c-b-r refresh) t wrp 15 15 ns 14 w to ras hold time(c-b-r refresh) t wrh 8 8 ns 14 output data hold time t doh 10 10 ns 14 output buffer turn off delay time from ras t rez 3 13 3 15 ns 6.11.12 output buffer turn off delay time from w t wez 3 18 3 20 ns 6.11.14 w to data delay t wed 20 20 ns 14 oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width(hyper page cycle) t wpe 5 5 ns pde to valid pd bit t pd 10 10 ns pde to pd bit inactive t pdoff 2 7 2 7 ns present detect read cycle ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v . see notes 1,2.)
dram module kmm372f213ck/cs notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are vih/vil. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transi- tion times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 1 ttl loads and 100pf. voh=2.0v and vol=0.8v. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min) and t awd 3 t awd (min), then the cycle is a read-write cycle and the data output will contain data read from the selected address. if neither of the above conditions are satisfied, the condition of the data out is indeterminated. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles and to the w leading edge in read-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . t cez (max), t rez (max), t wez (max) and t oez (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. if ras goes to high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes to high before ras high going , the open circuit condi- tion of the output is achieved by ras high going. t asc 3 t cp min the timing skew from the dram to the dimm resulted from the addition of buffers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 12. 13. 11. 14.
dram module kmm372f213ck/cs ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t oez t cez t wez dq t olz t cac
dram module kmm372f213ck/cs t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq
dram module kmm372f213ck/cs note : d out = open write cycle ( oe controlled write ) ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp don t care undefined cas v ih - v il - t rwl t cwl t dh t oeh t oed data-in t ds
dram module kmm372f213ck/cs read - modify - write cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address t olz
dram module kmm372f213ck/cs t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq t oep column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t oez t oea t oep t aa t cac t oea t aa t cpa t cac t cpa valid data-out valid data-out t oez t clz t rac t oea t olz t cac t rrh t cho t rez t oez t cac t och t cpa t cac valid data-out ? t asc t aa
dram module kmm372f213ck/cs ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc
dram module kmm372f213ck/cs don t care hyper page read-modify-write cycle undefined ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - row addr t csh t rasp t rp t asr t rah t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t rac t oea t clz t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed t rwl t crp t ds t oez valid data-out valid data-in valid data-out valid data-in t ds dq t rsh t olz t olz t hprwc t cac t aa
dram module kmm372f213ck/cs hyper page read and write mixed cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq t wez t cp t cp t hpc t hpc t hpc t rad t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea read( t cac ) read( t cpa ) write read( t aa )
dram module kmm372f213ck/cs don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq t wrp t wrh w v ih - v il - t rp * in ras -only refresh cycle of 64mb a-dile & b-die, when cas signal transits from low to high, the valid data may be cut off.
dram module kmm372f213ck/cs hidden refresh cycle ( read ) t oez data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq t wrh t rrh column address t oea t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t olz t wrp
dram module kmm372f213ck/cs t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp
dram module kmm372f213ck/cs cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t rez t clz write cycle v ih - v il - data-in dq t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in note : this timing diagram is applied to all devices besides 64m dram based modules. t cez t wez
dram module kmm372f213ck/cs open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t cez v oh - v ol - dq t wts t wth w v ih - v il - t chr t rp t ras
dram module kmm372f213ck/cs package dimensions 5.250 5.014 units : inches (millimeters) 0.050 0.039 .002 0.01max (0.25 max) 0.100max (2.54max ) 0.050 0.0039 (1.270 0.10) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c .118dia .004 (3.000dia .100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 1 . 0 0 0 ( 2 5 . 4 0 ) 0.118 (3.000) 0.250 (6.350 ) detail a 0.123 .005 (3.125 .125) 0.250 (6.350 ) detail b 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) 0.079 .0040 (2.000 .100) 0 . 1 1 8 ( 3 . 0 0 0 ) 0 . 2 0 0 m i n ( 5 . 0 8 m i n ) ( back view ) ( front view ) tsop 0.200max (5.08max ) soj tolerances : .005(.13) unless otherwise specified the used device is 2mx8 dram with edo mode, soj or tsop ii. (forward) dram part no. : kmm372f213ck/cs - km48v2104ck and km48v2104cs.

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